When: Jan 23, 2014
Where: Houston, TX, USA
What: The Society of HPC Professionals (SHPCP) Lunch and Learn Round Table Event
SHPCP is a Texas non-profit corporation established in 2009 to provide HPC professionals with an organization that will coordinate and conduct open forum meetings that address the use, availability and evaluation of existing technology and introduce emerging technology to the HPC community. Dan Cyca, Acceleware CTO, will be presenting at the society’s next lunch and learn, Optimizing RTM for Xeon Phi: Lessons Learned. Registration is free and open to non-members.
Optimizing RTM for Xeon Phi: Lessons Learned
In this presentation we will share our experience in porting and optimizing a commercial Reverse Time Migration (RTM) library to a cluster of Xeon Phi Coprocessors. The talk will focus on the different techniques needed to efficiently run real world data, as well as the similarities of optimizing a TTI propagation kernel for Xeon Phi and Xeon Sandy Bridge. The case study highlights the importance of fully utilizing the processing cores as well as the vector units within each core. We will demonstrate how parallel computation is obtained by tuning the OpenMP pragmas and the auto-vectorizer. Further speed improvements are obtained by implementing thread affinity for multi-tasking and fine tuning the memory access patterns for optimal data throughput. The second part of the presentation will focus on how to achieve linear scaling across multiple devices, which is critical when dealing with real-world RTM problems.
Dan Cyca, Chief Technology Officer, Acceleware Ltd.
Dan has extensive experience in developing technical software for multi-core platforms including GPUs, CPUs, FPGAs and Intel’s recent MIC architecture. Dan joined Acceleware in 2004 as a software developer to build the company’s first product. Since then, he has served in many technical and leadership roles in the company. Most recently, as the Director of Engineering, Dan was responsible for managing the development of Acceleware’s high performance seismic software libraries. Prior to Acceleware, Dan’s experience included developing 'C-to-hardware' compilers, and implementing digital signal processing and encryption algorithms on FPGAs. Dan has an M. Sc. in Electrical Engineering from the University of Calgary.