Where: Leipzig, Germany
Date: June 16-20, 2013
Join us in Leipzig, Germany June 16-20 to learn about the latest advancements in HPC. Stop by the Acceleware booth to meet the team and find out about:
HPC Programmer Training
- OpenCL (for GPUs and FPGAs)
- Optimization Training for Intel Xeon Phi Coprocessors – NEW!
- HPC Application Development
- Code Optimization
- Algorithm Design
Acceleware Software Libraries
- Seismic Imaging
Optimizing Commercial Seismic Exploration Software for Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors.
Wednesday, June 19, 3:00pm Intel Booth
Reverse Time Migration (RTM) is the state-of-the-art in full wave seismic depth imaging with a heavy compute cost using conventional CPUs. The Xeon Phi presents an opportunity to reduce overall hardware and power requirements. In this presentation we will share our experience optimizing Acceleware’s commercial anisotropic RTM library for Xeon and Xeon Phi. Optimization techniques and key performance results will be discussed.
Presented by Dan Cyca