ISC 2013 in Leipzig, Germany

Where: Leipzig, Germany
Date: June 16-20, 2013
Booth: 614
Website: isc-events.com/isc13

Join us in Leipzig, Germany June 16-20 to learn about the latest advancements in HPC. Stop by the Acceleware booth to meet the team and find out about:

HPC Programmer Training

  • CUDA
  • OpenCL (for GPUs and FPGAs)
  • OpenMP
  • MPI
  • Optimization Training for Intel Xeon Phi Coprocessors – NEW!

Consulting Services

  • HPC Application Development
  • Code Optimization
  • Algorithm Design

Acceleware Software Libraries

  • Electromagnetics
  • Seismic Imaging

Technical Presentations

Optimizing Commercial Seismic Exploration Software for Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors.

Wednesday, June 19, 3:00pm Intel Booth

Reverse Time Migration (RTM) is the state-of-the-art in full wave seismic depth imaging with a heavy compute cost using conventional CPUs. The Xeon Phi presents an opportunity to reduce overall hardware and power requirements. In this presentation we will share our experience optimizing Acceleware’s commercial anisotropic RTM library for Xeon and Xeon Phi. Optimization techniques and key performance results will be discussed.

Technical presentation by Dan Cyca

Presented by Dan Cyca
Chief Technology Officer, Acceleware Ltd.
Regarded as a leading mind in the field of parallel processing, Dan has extensive experience working with GPUs, clusters and multi-core solutions. Dan joined Acceleware in 2004 as a software developer to build the company’s first product. Since then, he has served in many technical and leadership roles in the company. Most recently, as the Director of Engineering, Dan was responsible for managing the software development group. Prior to Acceleware, Dan’s experience included developing 'C-to-hardware' compilers, and implementing digital signal processing and encryption algorithms on FPGAs. Dan has an M. Sc. in Electrical Engineering from the University of Calgary.