2015 GTC in San Jose

Visit Us at the GPU Technology Conference

When: March 17-20, 2015
Where: San Jose, California
Booth: #612
What: NVIDIA’s GTC is the place to learn, share and discover what’s next for the future of high performance computing. Over 500 sessions, tutorials and hands-on programming labs it offers unmatched opportunities.

Discover the latest advances in GPU technology and how scientists, developers, graphic artists, engineers and IT managers are using it to tackle their day-to-day computational and graphics challenges.

Explore the exhibit hall, your one stop shop for the hottest information on GPU-enabled applications, developer tools and hardware systems.

Improve your programming skills with a great selection of tutorials and programming labs led by industry experts and NVIDIA engineers!


Acceleware Tutorials at GTC

Back by popular demand, Acceleware will be teaching the following CUDA tutorials at the conference. A printed copy of the tutorial will be available for all attendees. Attend all sessions and collect all four!

Session 1 of 4: An Introduction to CUDA Programming (S5661)

Presented by Chris Mason - Tuesday March 17th at 1:00PM
Join us for an informative introductory tutorial intended for those new to CUDA and is the foundation for our following three tutorials. Those with no previous CUDA experience will leave with essential knowledge to start programming in CUDA. For those with previous CUDA experience, this tutorial will refresh key concepts required for subsequent tutorials on CUDA optimization.

Session 2 of 4: An Introduction to the GPU Memory Model (S5662)

Presented by Chris Mason - Tuesday March 17th at 3:00PM
This tutorial is for those with a basic understanding of CUDA who want to learn about the GPU memory model and optimal storage locations. To learn the basics of CUDA programming required for this session, attend the session entitled An Introduction to GPU Programming. This session begins with an essential overview of the GPU architecture and thread cooperation before focusing on different memory types available on the GPU.

Session 3 of 4: Asynchronous Operations & Dynamic Parallelism in CUDA (S5663)

Presented by Dan Cyca - Wednesday March 18th at 9:30AM
This tutorial builds on the two previous sessions (An Introduction to GPU Programming and the Introduction to GPU Memory Model) and is intended for those with a basic understanding of CUDA programming. This tutorial dives deep into asynchronous operations and how to maximize throughput on both the CPU and GPU with streams. We will demonstrate how to build a CPU/GPU pipeline and how to design your algorithm to take advantage of asynchronous operations. The second part of the session will focus on dynamic parallelism.A programming demo involving asynchronous operations will be delivered.

Session 4 of 4: Essential CUDA Optimization Techniques (S5664)

Presented by Dan Cyca - Wednesday March 18th at 2:00PM
This tutorial is for those with some background in CUDA including an understanding of the CUDA memory model and streaming multiprocessor. Our earlier tutorials will provide the background information necessary for this session. This informative tutorial will provide an overview of the analysis performance tools and key optimization strategies for compute, latency and memory bound problems.


Acceleware Talk at GTC

Justifying Reverse Time Migration Order of Accuracy on NVIDIA GPUs (S5350)

Presented by Marcel Nauta - Thursday, March 19th at 10:30AM
Theoretical Full Wave Modelling improvements present compromises between various hardware metrics such as computational intensity, GPU/CPU memory usage, and hard disk requirements. Varying the spatial order of accuracy changes a kernel from memory bound to compute bound and strongly affects register usage. This non-linear relationship between compute cost and order of accuracy determines the optimal configuration on a given hardware architecture.


Presenters

Acceleware training instructor Chris Mason

Chris Mason

Product Manager, Acceleware Ltd.
Chris is the Product Manager for Acceleware's GPU accelerated electromagnetic product line. He is responsible for the successful development and launch of Acceleware products used by companies world-wide. Chris has 9 years of experience in developing commercial applications for the GPU and has delivered over 20 CUDA courses to students in a diverse range of industries. His previous experience also includes parallelization of algorithms on digital signal processors (DSPs) for cellular phones and base stations. Chris has a Masters in Electrical Engineering from Stanford University.

   
Technical presentation by Dan Cyca

Dan Cyca

Chief Technology Officer, Acceleware Ltd.
Dan has extensive experience working with GPUs, clusters and multi-core solutions. He is responsible for the development of Acceleware's high performance software applications for the engineering and energy industries. Dan joined Acceleware in 2004 as a software developer to build the company's first product, an electromagnetic solver for the GPU. Dan has also played a fundamental role in developing Acceleware's CUDA training materials and teaching the content to companies around the world. Prior to Acceleware, Dan's experience included developing 'C-to-hardware' compilers, and implementing digital signal processing and encryption algorithms on FPGAs. Dan has an M. Sc. in Electrical Engineering from the University of Calgary.

   
Presentation by Marcel Nauta

Marcel Nauta

Software Developer
Marcel joined Acceleware in 2012 to advance the company's high performance seismic software for multi-core CPUs and NVIDIA GPUs. His areas of expertise include analysis and implementation of numerical algorithms for electromagnetic and seismic wave equations. Marcel has a published a number of technical papers on advanced finite-difference time-domain methods and was awarded the NSERC CGS-M for his Masters. He currently holds an AITF Industry Associates award for his research at Acceleware. Marcel has a B. Sc. in Physics and a M. Sc. in Electrical Engineering from the University of Calgary.